Profile

Career

1985.03	Master of Electronic Engineering at Graduate School of Seoul National University
⁠1993.02	Doctor of Electronic Engineering at Graduate School of Seoul National University
⁠1983.03	1985.02 Researcher of exchange research department at Electronics and Telecommunications Research Institute
⁠1987.03	Professor of Changwon National Universty
⁠1995.01	2010.02 IEEE Changwon Section Chair
⁠1998.02	1999.08 Ancaster University visiting professor
⁠2003.09	2004.08 Director of the Faculty of Professors at Changwon University
⁠2003.05	2005.06 Director of Startup Nursing Center at Changwon University, Director of Startup Nursing Association
⁠2003.10	Director of SoC Center at Changwon University
⁠2004.06	2009.12 Head of the Intelligent Home Business Group at Changwon University
⁠2004.10	2005.12 Chairperson of Technical Road Map Working Committee of Intelligent Home Specialized Industry
⁠2008.03	2009.05 Director of NURI Business Group
⁠2009.09	2013.02 Director of BK Business Group
⁠2013.03	Director of Information and Computing at Changwon University, Director of the Management Committee of Educational Computing Network

Prime

⁠2007.03	a citation at Changwon University
⁠2008.11	Mechatronics Research Director's Performance Appraisal Board
⁠2009.11	Patent Office Gold Award (Startup Circuit and Band Gap Reference Voltage Generator)
⁠2010.01	ICICTES 2010 Award for Excellence in International Studies
⁠2010.03	Third Eastern HiTec Design Competition Award
⁠2013.06	Award of Excellence in the Korean Electronics Engineering Association
⁠2014.06	Award of Excellence in the Korean Electronics Engineering Association

Thesis

• 1Charge pump design for TFT-LCD driver IC using stack-MIM capacitor, IEICE Trans. Electron., vol. E91-C, no. 5, pp. 928-935, June 2008
• 2Low-power 512-bit EEPROM designed for UHF RFID tag chip, ETRI Journal, vol. 30, no. 3, pp. 347-354, June 2008
• 3Design of asynchronous multi-bit OTP memory, IEICE Trans. Electron., vol. E92-C, no. 1, pp. 173-177, January 2009
• 4Design of small-area multi-bit antifuse-type 1k-bit OTP memory, J. Cent. South Univ. Technolo., vol. 16, no. 3, pp. 467-473, June 2009
• 5Power management unit chip design for automobile active-matrix light-emitting diode display module, J. Cent. South Univ. Technolo., vol. 16, n o. 4, pp. 621-628, August 2009
• 6Design and measurement of a 1-kbit eFuse one-time programmable memory IP based on a BCD process, IEICE Trans. Electron., vol. E93-C, no. 8, pp. 1365-1370, August 2010
• 7Design of logic process based low-power 512-bit EEPROM for UHF RFID tag, chip, J. Cent. South Univ. Technolo., vol. 17, no. 5, pp. 1011-1020, October 2010
• 8Design of an EEPROM for a MCU with the wide voltage range, Journal of Semiconductor, vol. 10, no. 4, pp. 316-325,
  December 2010
• 9Design of 1 kbit antifuse one time programmable memory IP using dual program voltage, J. Cent. South Univ.Technolo., vol. 18, no. 1, pp. 125-132, February 2010
• 10Design of 1-kb eFuse OTP memory IP with reliability considered, Journal of Semiconductor, vol. 16, no. 3, pp. 88-94, June 2011
• 11Design of 512-bit logic process-baced single poly EEPROM IP, J. Cent. South Univ. Technolo., vol. 18, no. 6, pp. 2036-2044, December 2011
• 12Design of an 8-bit differential paired OTP mewmory IP reducing sensing resistance, J. Cent. South Univ.Technolo., vol. 19, no. 1, pp. 168-173, January 2011
• 13Design of small-area and high-efficiency DC-DC converter for 1T-SRAM, J. Cent. South Univ. Technolo., vol. 19, no. 2, pp. 417-423, February 2012
• 14Design of 256 bit single-poly MTP memory based on BCD process,J. Cent. South Univ. Technolo., vol. 19, no. 12, pp. 3460-3467, December 2012
• 15Design of 32 kbit one-time programmable memory for microcontroller units, J. Cent. South Univ. Technolo., vol. 19, no. 12, pp. 3475-3483, December 2012
• 16Design of 32-bit differential paired eFuse OTP memory in a form of two-dimmensional array, J. Cent. South Univ. Technolo., vol. 19, no. 12, pp. 3484-3491, December 2012